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1 high speed, dual channel, 6a, 4.5 to 16v out , power mosfet driver isl89160, isl89161, isl89162 the isl89160, isl89162, and isl89162 are high-speed, 6a, dual channel mosfet drivers. these parts are identical to the isl89163, isl89164, isl89165 drivers but without the enable inputs for each channel. two input logic thresholds are available: 3.3v (cmos and ttl compatible) and 5.0v (cmos). precision thresholds on all logic inputs allow the use of external rc circuits to generate accurate and stable time delays on both inputs, ina and inb. this capabilit y is very useful for dead time control. at high switching frequencies, these mosfet drivers use very little bias current. separate, non-overlapping drive circuits are used to drive each cmos output fet to prevent shoot-thru currents in the output stage. the undervoltage lock-out (uv) insures that driver outputs remain off (low) until vdd is sufficiently high for correct logic control. this prevents unexpected behavior when v dd is being turned on or turned off. features ? dual output, 6a peak current (sink and source) ?typical on-resistance <1 ? specified miller plateau drive currents ? very low thermal impedance ( jc = 3 c/w ) ? 3.3v and 5v logic inputs with hysteresis are vdd tolerant ? precision threshold inputs for time delays with external rc components ? ~ 20ns rise and fall time driving a 10nf load. ? low operating bias currents ?pb-free (rohs compliant) applications ? synchronous rectifier (sr) driver ? switch mode power supplies ? motor drives, class d amplifiers, ups, inverters ? pulse transformer driver ? clock/line driver figure 1. typical application figure 2. temperature stable logic thresholds 8 6 7 1 4 3 2 5 epad v dd 4.7f ina inb gnd outa outb nc nc -40 5 20 35 50 65 80 95 125 temperature (c) option b thresholds (5v) positive threshold negative threshold -25 10 110 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 january 20, 2011 fn7719.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl89160, isl89161, isl89162 2 fn7719.1 january 20, 2011 block diagram outx v dd inx gnd for clarity, only one channel is shown epad for proper thermal and electrical performance, the epad must be connected to the pcb ground plane. separate fet drives, with non-overlapping outputs, prevent shoot-thru currents in the output cmos fets resulting with very low high frequency operating currents. isl89161, isl89162 isl89160 10k for options a and b, the uv comparator holds off the outputs until v dd ~> 3.3v dc . pin configurations isl89160fr, isl89160fb (8 ld tdfn, epsoic) top view isl89161fr, isl89161fb (8 ld tdfn, epsoic) top view isl89162fr, isl89162fb (8 ld tdfn, epsoic) top view ina gnd inb outb outa nc nc vdd 8 6 7 1 4 3 2 5 /ina gnd /inb outb outa nc nc vdd 8 6 7 1 4 3 2 5 /ina gnd inb outb outa nc nc vdd 8 6 7 1 4 3 2 5 pin descriptions pin number symbol description 1, 8 nc no connect. this pin may be left open or connected to 0v or vdd 2 ina or /ina channel a input, 0v to vdd 3 gnd power ground, 0v 4 inb or /inb channel b enable, 0v to vdd 5 outb channel b output 6 vdd power input, 4.5v to 16v 7 outa channel a output, 0v to vdd epad power ground, 0v
isl89160, isl89161, isl89162 3 fn7719.1 january 20, 2011 ordering information part number (notes 1, 2, 3) part marking temp range (c) input configuration input logic package (pb-free) pkg. dwg. # isl89160frtaz 160a -40 to +125 non-inverting 3.3vdc 8 ld 3x3 tdfn l8.3x3i isl89161frtaz 161a -40 to +125 inverting 8 ld 3x3 tdfn l8.3x3i isl89162frtaz 162a -40 to +125 inverting + non-inverting 8 ld 3x3 tdfn l8.3x3i isl89160fbeaz 89160 fbeaz -40 to +125 non-inverting 8 ld epsoic m8.15d isl89161fbeaz 89161 fbeaz -40 to +125 inverting 8 ld epsoic m8.15d isl89162fbeaz 89162 fbeaz -40 to +125 inverting + non-inverting 8 ld epsoic m8.15d isl89160frtbz 160b -40 to +125 non-inverting 5.0vdc 8 ld 3x3 tdfn l8.3x3i isl89161frtbz 161b -40 to +125 inverting 8 ld 3x3 tdfn l8.3x3i isl89162frtbz 162b -40 to +125 inverting + non-inverting 8 ld 3x3 tdfn l8.3x3i ISL89160FBEBZ 89160 fbebz -40 to +125 non-inverting 8 ld epsoic m8.15d isl89161fbebz 89161 fbebz -40 to +125 inverting 8 ld epsoic m8.15d isl89162fbebz 89162 fbebz -40 to +125 inverting + non-inverting 8 ld epsoic m8.15d notes: 1. add ?-t*?, suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl89160, isl89161, isl89162 . for more information on msl, please see technical brief tb363 .
isl89160, isl89161, isl89162 4 fn7719.1 january 20, 2011 absolute maximum rating s thermal information supply voltage, v dd relative to gnd . . . . . . . . . . . . . . . . . . . . -0.3v to 18v logic inputs (ina, inb) . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v outputs (outa, outb) . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v average output current (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ma esd ratings human body model class 2 (tested per jesd22-a114e) . . . . . . . . 2000v machine model class b (tes ted per jesd22-a115-a) . . . . . . . . . . . . 200v charged device model class iv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latch-up (tested per jesd-78b; class 2, level a) output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 4, 5). . . . . . . . . 44 3 8 ld epsoic package (notes 4, 5) . . . . . . . 42 3 max power dissipation at +25c in free air . . . . . . . . . . . . . . . . . . . . . 2.27w max power dissipation at +25c with copper plane . . . . . . . . . . . . . 33.3w storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temp range . . . . . . . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp maximum recommended operating conditions junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage, v dd relative to gnd. . . . . . . . . . . . . . . . . . . . . .4.5v to 16v logic inputs (ina, inb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v dd outputs (outa, outb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v dd caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. the average output current, when driving a power mosfet or similar capacitive load, is the average of the rectified output cu rrent. the peak output currents of this driver are self limiting by transconductance or r ds(on) and do not required any external comp onents to minimize the peaks. if the output is driving a non-capacitive load, such as an led, maximum output current must be limited by external means to less than the specified absolute maximum. dc electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, unless otherwise specified. boldface limits apply over the operating junction te mperature range, -40c to +125c. parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7) power supply voltage range v dd --- 4.5 16 v v dd quiescent current i dd inx = gnd - 5 - - - ma ina = inb = 1mhz, square wave - 25 - - ma undervoltage v dd undervoltage lock-out (note 9) v uv ina = inb = true (note 10) -3.3- - - v hysteresis - ~25 - - - mv inputs (note 11) input range for ina, inb v in --- gnd v dd v logic 0 threshold for ina, inb (note 9) v il option a, nominally 37% x 3.3v -1.22- 1.12 1.32 v option b, nominally 37% x 5.0v -1.85- 1.70 2.00 v logic 1 threshold for ina, inb (note 9) v ih option a, nominally 63% x 3.3v -2.08- 1.98 2.18 v option b, nominally 63% x 5.0v -3.15- 3.00 3.30 v input capacitance of ina, inb (note 8) c in -2- - - pf
isl89160, isl89161, isl89162 5 fn7719.1 january 20, 2011 input bias current for ina, inb i in gnd isl89160, isl89161, isl89162 6 fn7719.1 january 20, 2011 miller plateau source current (see test circuit figure 6) i mp v dd = 10v, v miller = 5v -5.2- - - a i mp v dd = 10v, v miller = 3v -5.8- - - a i mp v dd = 10v, v miller = 2v -6.9- - - a ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, unless otherwise specified. boldface limits apply over the operating junction te mperature range, -40c to +125c. (continued) parameters symbol test conditions /notes t j = +25c t j = -40c to +125c units min typ max min max test waveforms and circuits figure 3. prop delays and matching figure 4. rise/fall times figure 5. miller plateau sink current test circuit fig ure 6. miller plateau source current test circuit ina, inb outa outb 0v 3.3v* t rdly t rdly 50% 50% t fdly t fdly * logic levels: a option = 3.3v, b option = 5.0v t rm t fm /outb /outa outa or outb t r t f 90% 10% v miller 10v +i sense -i sense 10f 0.1f 0.1 200ns 10k isl8916x 10nf v miller 10v +i sense -i sense 10f 0.1f 0.1 200ns 10k isl8916x 10nf
isl89160, isl89161, isl89162 7 fn7719.1 january 20, 2011 figure 7. miller plateau sink current fi gure 8. miller plateau source current test waveforms and circuits (continued) 200ns v miller -i mp v out current through 0.1 resistor 10v 0a 0v 200ns v miller i mp v out current through 0.1 resistor 0 typical performance curves figure 9. i dd vs v dd (static) figure 10. i dd vs v dd (1 mhz) figure 11. i dd vs frequency (+25c) figure 12. r ds(on) vs temperature 2.0 2.5 3.0 3.5 4 8 12 16 static bias current (ma) v dd +125c +25c -40c 20 25 30 35 15 10 5 4 8 12 16 1mhz bias current (ma) v dd +125c +25c -40c 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 2.0 frequency (mhz) i dd (ma) no load 5v 10v 16v 12v 1.8 1.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -45 -20 5 30 55 80 105 130 r ds(on) ( ) temperature (c) v out low v out high
isl89160, isl89161, isl89162 8 fn7719.1 january 20, 2011 functional description overview the isl89160, isl89161, isl89162 drivers incorporate several features including precision inpu t logic thresholds, undervoltage lock-out, and fast rising high output drive currents. the precision input thresholds faci litate the use of an external rc network to delay the rising or falling propagation of the driver output. this is a useful feature to create dead times for bridge applications to prevent shoot through. to prevent unexpected glitches on the output of the isl89160, isl89161, isl89162 during power-on or power-off when v dd is very low, the undervoltage (uv) lock-out prevents the outputs of the isl89160, isl89161, isl89162 driver from turning on. the uv lock-out forces the driver outputs to be low when vdd < ~3.2 vdc regardless of the input logic level. the fast rising (or falling) output drive currents of the isl89160, isl89161, isl89162 minimize the turn-on (off) delays due to the input capacitance of the driven fet. the switching transition period at the miller plateau is also minimized by high drive currents even at these lower output voltages. (see the specified miller plateau currents in the ac electrical specifications on page 5). application information precision thresholds for time delays for input logic voltage option a, the nominal input negative transition threshold is 1.22v and the positive tran sition threshold is 2.08v (37% and 63% of 3.3v) li kewise, for input logic option b, the nominal input negative transition threshold is 1.85v and the positive transition threshold is 3.15v (37% and 63% of 4.0v). in figure 15, r del and c del delay the rising edge of the input signal. for the falling edge of the input signal, the diode shorts out the resistor resulting in a mi nimal falling edge delay. if the diode polarity is reversed, the falling edge is delayed and the rising delay is minimal. the 37% and 63% thresholds were chosen to simplify the calculations for the desired time delays. when using an rc circuit to generate a time delay, the delay is simply t (secs) = r (ohms) x c (farads). please note th at this equation only applies if the input logic voltage amplitude is 3.3v. if the logic high amplitude is higher than 3.3v, the equations in equation 1 can be used for more precise delay calculations. in this example, the high input logic voltage is 5v, the positive threshold is 63% of 3.3v and the low level input logic is 0.1v. note the rising edge propagation delay of the driver must be added to this value . the minimum recommended value of c is 100pf. the parasitic capacitance of the pcb and any attached scope probes will introduce significant delay errors if smaller values are used. larger values of c will further minimize errors. acceptable values of r are primarily effected by the source resistance of the logic inputs. generally, 100 resistors or larger are usable. a practica l maximum value, limited by contamination on the pcb, is 1m . figure 13. output rise/fall time figure 14. propagation delay vs v dd typical performance curves (continued) 15 20 25 -45 -20 5 30 55 80 105 130 rise/fall time (ns) temperature (c) fall time, c load = 10nf rise time, c load = 10nf 15 20 25 30 579111315 propagation delay (ns) v dd output falling prop delay output rising prop delay inx r del c del d outx figure 15. delay using rcd network v h 5v = v thresh 63% 3.3v = v l 0.1v = r del 100 = c del 1nf = t del r del c del ? ln v l v thresh ? v h v l ? -------------------------------------- - 1 + ?? ?? ?? = t del 51.731ns = high level of the logic signal into the rc positive going threshold low level of the logic signal into the rc timing values nominal delay time (eq. 1)
isl89160, isl89161, isl89162 9 fn7719.1 january 20, 2011 power dissipation of the driver the power dissipation of the isl89160, isl89161, isl89162 is dominated by the losses associated with the gate charge of the driven bridge fets and the switch ing frequency. the internal bias current also contributes to the total dissipation but is usually not significant as compared to the gate charge losses. figure 16 illustrates how the gate charge varies with the gate voltage in a typical power mosfet. in this example, the total gate charge for v gs = 10v is 21.5nc when v ds = 40v. this is the charge that a driver must source to turn-on the mosfet and must sink to turn-off the mosfet. equation 2 shows calculating the power dissipation of the driver: where: freq = switching frequency, v gs = v dd bias of the isl89160, isl89161, isl89162 q c = gate charge for v gs i dd (freq) = bias current at the switching frequency (see figure 9) r ds(on) = on-resistance of the driver r gate = external gate resistance (if any). note that the gate power dissipation is proportionally shared with the external gate resistor and the output r ds(on) . when sizing an external gate resistor, do not overlook the power dissipated by this resistor. typical application circuit this is an example of how the isl89160, isl89161, isl89162, mosfet drivers can be applied in a zero voltage switching full bridge. two main signals are required: a 50% duty cycle square wave (sqr) and a pwm signal synchronized to the edges of the sqr input. an isl89162 is used to drive t1 with alternating half cycles driving q ul and q ur . an isl89160 is used to drive q ll and q lr also with alternat ing half cycles. unlike the two high-side bridge fets, the two low side bridge fets are turned on with a rising edge delay. the delay is setup by the rcd network on the inputs to the isl89160. the duration of the delay is chosen to turn on the low-side fets when the voltage on their respective drains is at the resonant valley. for a complete description of the zvs topology, refer to an1603 ?isl6752_54 evaluation board application note?. q g, gate charge (nc) 12 10 8 6 4 2 0 024681012141618202224 v gs gate-source voltage (v) figure 16. mosfet gate charge vs gate voltage v ds = 64v v ds = 40v (eq. 2) p d 2q c freq v gs r gate r gate r ds on () + ------------------------------------------ i dd freq () v dd ? + ? ? ? ? = v ll pwm lr ll ll red dashed lines emphasize the resonant switching delay of the low-side bridge fets zvs full bridge t1a t1b t2 u1b u2a u2b q ul q ur q ll q lr ll lr v lr sqr sqr r v gll v gul v glr v gur v glr v gul v gur v gll v bridge isl89162 u1a ? isl89160 ? isl89160 ll: lower left lr: lower right ul: upper left ur: upper right gll: gate lower left
isl89160, isl89161, isl89162 10 fn7719.1 january 20, 2011 general pcb layout guidelines the ac performance of the isl89160, isl89161, isl89162 depends significantly on the de sign of the pc board. the following layout design guidelines are recommended to achieve optimum performance: ? place the driver as close as possible to the driven power fet. ? understand where the switching power currents flow. the high amplitude di/dt currents of the driven power fet will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they are usually more effective than parallel traces. ? avoid paralleling high amplitude di/dt traces with low level signal lines. high di/dt will in duce currents and consequently, noise voltages in the low level signal lines. ? when practical, minimize impe dances in low level signal circuits. the noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. ? be aware of magnetic fields em anating from tr ansformers and inductors. gaps in these structures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. ? the use of low inductance components such as chip resistors and chip capacitors is highly recommended. ? use decoupling capacitors to reduce the influence of parasitic inductance in the vdd and gnd leads. to be effective, these caps must also have the shortest possible conduction paths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resistance to dampen resonating parasitic circuits especially on outa and outb. if an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for control circuits that source the input signals to the isl89160, isl89161, isl89162. ? avoid having a signal ground plane under a high amplitude dv/dt circuit. this will inject di/dt currents into the signal ground paths. ? do power dissipation and voltag e drop calculations of the power traces. many pcb/cad programs have built in tools for calculation of tr ace resistance. ? large power components (power fets, electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components especially parasitic inductance. general epad heatsinking considerations the thermal pad is electrically connected to the gnd supply through the ic substrate. the epad of the isl89160, isl89161, isl89162 has two main functions: to provide a quiet gnd for the input threshold comparators and to provide heat sinking for the ic. the epad must be connected to a ground plane and no switching currents from the driv en fet should pass through the ground plane under the ic. figure 17 is a pcb layout example of how to use vias to remove heat from the ic through the epad. for maximum heatsinking, it is recommended that a ground plane, connected to the epad, be added to both sides of the pcb. a via array, within the area of the epad, will conduct heat from the epad to the gnd plane on the bottom layer. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the isl89160, isl89161, isl89162, the air flow and the maximum temperature of the air around the ic. epad gnd plane component layer epad gnd plane bottom layer figure 17. typical pcb pattern for thermal vias
isl89160, isl89161, isl89162 11 fn7719.1 january 20, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl89160, isl89161, isl89162 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 1/13/11 fn7719.1 removed option c reference from visio graphics due to parts not releasing yet. 1/12/11 converted to new intersil template updated page 1 graphic by depicting 2 lines showing posi tive threshold and 2 lines showing negative threshold: page 1 - updated copyright to include 2011 page 1 - removed related literature from due to documentation being nonexistent at this time. page 2 - updated pin description table by placing both pin numbers 1 and 8 on same line page 3 - updated ordering information by adding option b parts page 4 - added note reference to inputs section in electrical spec table page 5 - changed note in electrical spec table from: parameters with min and/or max limits are 100% tested at +25c, un less otherwise specified. temperature limits established by characterizati on and are not production tested. to: compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. 11/2/10 fn7719.0 initial release
isl89160, isl89161, isl89162 12 fn7719.1 january 20, 2011 package outline drawing l8.3x3i 8 lead thin dual flat no-lead plastic package rev 1 6/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 index area 6x 0.65 1.64 +0.10/ - 0.15 8 1 8x 0.400 0.10 6 max 0.80 see detail "x" 0.08 0.10 c c c ( 2.80 ) (1.64) ( 8 x 0.30) ( 8x 0.60) ( 2.38 ) ( 1.95) 2.38 0.10 8x 0.30 a mc b 4 2x 1.950 +0.10/ - 0.15 (6x 0.65) 4 5 pin 1
isl89160, isl89161, isl89162 13 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7719.1 january 20, 2011 for additional products, see www.intersil.com/product_tree small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15d 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.059 0.067 1.52 1.72 - a1 0.003 0.009 0.10 0.25 - b 0.0138 0.0192 0.36 0.46 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.811 3.99 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.019 0.25 0.50 5 l 0.016 0.050 0.41 1.27 6 n8 87 0 8 0 8 - p 0.118 0.137 3.00 3.50 11 p1 0.078 0.099 2.00 2.50 11 rev. 0 5/07 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.

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